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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD6122 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 cdma 3 v transmitter if subsystem with integrated voltage regulator functional block diagram i input q input local oscillator input attenuator low dropout regulator common-mode reference output vreg power- down 1 1.23 v reference output vpos temperature compensation gain control scale factor gain control voltage input gain control reference voltage input transmit output if amplifiers quadrature modulator power- down 2 if amplifier input quadrature modulator output 4 2 AD6122 vcc features fully compliant with is98a and pcs specifications linear if amplifier C63 db to +34 db linear-in-db gain control temperature-compensated gain control quadrature modulator modulates ifs from 50 mhz to 350 mhz integral low dropout regulator accepts 2.9 v to 4.2 v input from battery low power 10.4 ma at midgain <10 m a sleep mode operation applications cdma, w-cdma, amps and tacs operation qpsk transmitters general description the AD6122 is a low power if transmitter subsystem, specifi- cally designed for cdma applications. it consists of an i and q modulator, a divide-by-two quadrature generator, high dynamic range if amplifiers with voltage-controlled gain and a power- down control input. an integral low dropout regulator allows operation from battery voltages from 2.9 v to 4.2 v. the gain control input accepts an external gain control voltage input from a dac. it provides 97 db of gain control with a nominal 75 db/v scale factor. either an internal or an external reference may be used to set the gain-control scale factor. the i and q modulator accepts differential quadrature base- band inputs from a cdma baseband converter. the local oscil- lator is injected at twice the if frequency. a divide-by-two quadrature generator followed by dual polyphase filters ensures 1 quadrature accuracy. the modulator provides a common-mode reference output to bias the transmit dacs in the baseband converter to the same common-mode voltage as the modulator inputs, allowing dc coupling between the two ics and thus eliminating the need to charge and discharge coupling capacitors. this allows the fastest power-up and power-down times for the AD6122 and cdma baseband ics. the AD6122 is fabricated using a 25 ghz f t silicon bicmos process and is packaged in a 28-lead ssop.
rev. 0 C2C AD6122Cspecifications (t a = +25 8 c, v cc = +3.0 v, lo = 2 3 if, refin = 1.23 v, ldo enabled, unless otherwise noted) note: all powers shown in dbm are referred to 1 k v . specification conditions min typ max units modulator lo = 260.76 mhz (2 if), 100 mv p-p 500 mv p-p differential i and q inputs; output level output level referred to a 1 k w differential load C21 dbm output third order harmonic C50 dbc i/q inputs differential input voltage differential 500 mv p-p bandwidth C3 db 20 mhz resistance 2k w quadrature accuracy 1 amplitude balance 0.1 db output referred noise 0.9 mhz to 5.0 mhz offsets C169 dbm/hz modulator common-mode reference 1.408 v lo input resistance differential input at 260.38 mhz 1.2 k w lo input capacitance differential input at 260.38 mhz 2.4 pf lo carrier leakage bias i/q using modcmref C40 dbc if amplifier f if = 130.38 mhz noise figure vgain = 2.5 v, 1 k w differential load 10 db input 1 db compression point vgain = 2.5 v C32 dbm input third-order intercept vgain = 2.5 v C24 dbm gain flatness if 630 khz 0.25 db input capacitance shunt equivalent model at 130.38 mhz 2.3 pf differential if input resistance shunt equivalent model at 130.38 mhz 680 w differential if output resistance per pin at 130.38 mhz 4.2 k w differential if output capacitance per pin at 130.38 mhz 2.0 pf gain control interface gain scaling using internal reference 75 db/v gain scaling linearity for a typical dynamic range of 92 db 3 db/v minimum gain vgain = 0.5 v C63 db maximum gain vgain = 2.5 v +34 db gain control response time 90 db gain change, min gain to max gain 0.7 m s input resistance at refin 10 m w input resistance at vgain 109 k w power-down interface logic threshold high power-up on logical high 1.34 v logic threshold low 1.30 v input current for logical high 0.1 m a turn-on response time measure to settling of agc from standby mode 23 m s turn-off response time to 200 m a supply current 187 ns low dropout regulator external pnp pass transistor, vce sat = C0.4 v max, h fe = 100/300 min/max input range 2.9C4.2 v nominal output 2.70 v dropout voltage 200 mv reference output 1.23 v power supply supply range bypassing internal ldo 2.7C5.0 v supply current vgain = 1.5 v (unity gain) 10.4 ma standby current 7.8 m a operating temperature t min to t max C40 +85 c specifications subject to change without notice.
rev. 0 AD6122 C3C absolute maximum ratings 1 supply voltage dvcc, ifvcc, txvcc to dgnd, ifgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5 v internal power dissipation 2 . . . . . . . . . . . . . . . . . . . 600 mw operating temperature range . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering 60 sec) . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 thermal characteristics: 28-lead ssop package: q ja = 115.25 c/w. ordering guide temperature package model range package description option AD6122ars C40 c to +85 c shrink small outline package (ssop) rs-28 AD6122arsrl C40 c to +85 c 28-lead ssop on tape-and-reel pin configuration top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AD6122 ifgnd txvcc txopn txopp dvcc loipn loipp pd1 pd2 ldoe ldob dgnd ldognd ldoc ifinn ifinp modopn modopp qipp qipn modcmref vgain refin refout ifvcc iipn iipp ifgnd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD6122 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. 0 AD6122 C4C pin function descriptions pin # pin label description function 1 pd1 power-down 1 if amplifier power-down control input; cmos com- patible; high = entire ic powers down, low = if amplifiers on. 2 pd2 power-down 2 modulator power-down control input; cmos compat- ible; high = modulator off , low = modulator on. 3 ldoe low dropout regulator pass connects to emitter of external pnp pass transistor transistor emitter connection and vcc. 4 ldob low dropout regulator pass connects to base of external pnp pass transistor. transistor base 5 ldoc low dropout regulator pass connects to collector of external pnp pass transistor. transistor collector 6 ldognd low dropout regulator ground ground. 7 dgnd digital ground ground. 8 loipp local oscillator positive input connects to local oscillator; ac coupled. 9 loipn local oscillator negative input connects to ground via decoupling capacitor. 10 dvcc digital vcc connects to digital supply. 11 txopp transmit output positive connects to output filter; ac coupled. 12 txopn transmit output negative connects to output filter; ac coupled. 13 txvcc transmit output vcc connects to ldo output via decoupling network. 14 ifgnd if ground ground. 15 ifinn if input negative if negative input from lc roofing filter. 16 ifinp if input positive if positive input from lc roofing filter. 17 modopn modulator negative if output output modulator output to lc roofing filter. 18 modopp modulator positive output modulator output to lc roofing filter. 19 qipp q input positive connects to q positive output of baseband ic. 20 qipn q input negative connects to q negative output of baseband ic. 21 modcmref modulator common-mode connects to cdma baseband converter tx dac reference out common-mode reference input. 22 iipn i input negative connects to i negative output of baseband ic. 23 iipp i input positive connects to i positive output of baseband ic. 24 ifgnd ground connects to if ground. 25 ifvcc if vcc connects to decoupled output of ldo regulator. 26 refout gain control reference output provides 1.23 v voltage reference output for dac in cdma baseband converter and refin (pin 27). 27 refin gain control reference input accepts 1.23 v reference input from refout (pin 17) or external reference. 28 vgain gain control voltage input accepts gain control input voltage from external dac. max gain = 2.5 v; min gain = 0.5 v.
rev. 0 AD6122 C5C test figures 2 5 x1 v p ad830 i data C15v 0.1 m f modcmref a=1 vC1 x2 y1 y2 v n 1 3 4 +15v 0.1 m f 8 7 2 5 x1 v p ad830 C15v 0.1 m f modcmref a=1 x2 y1 y2 v n 1 3 4 +15v 0.1 m f 8 7 must be equal lengths 2 5 x1 v p ad830 q data C15v 0.1 m f modcmref a=1 x2 y1 y2 v n 1 3 4 +15v 0.1 m f 8 7 2 5 x1 v p ad830 C15v 0.1 m f modcmref a=1 x2 y1 y2 v n 1 3 4 +15v 0.1 m f 8 7 must be equal lengths AD6122 iipp iipn qipp qipn loipp lo input modcmref 10nf 10nf 0.1 m f mod_out vreg out 450 v 205 v 450 v 0.1 m f vreg out modopp modopn 50 v 50 v 50 v 50 v 50 v 50 v out out out out vC1 vC1 vC1 vC1 vC1 vC1 vC1 loipn figure 1. quadrature modulators characterization input and output impedance matches
rev. 0 AD6122 C6C mod out i channel q channel lo input if in rf source 1 aux meas port note: rf cables for i and q paths must be of equal length iftx out i data q data rf source 2 r&s fsea20/30 spectrum analyzer rf input r&s smt03 rf r&s smt03 rf hpe3610 power supply hp34970a data acquisition & switch control dc measurements & control bits to rf switches tektronix afg2002 500mvp-p differential test bed motherboard figure 3. general test set 10nf 10nf 0.1 m f vreg out 453 v 205 v 453 v 0.1 m f vreg out pull-up inductors chosen for peak response at the test frequency. 10nf 10nf noise source reactive conjugate match to noise filter meter 4:1 ifinn ifinp txopp txopn 1:8 AD6122 figure 4. if amplifiers noise figure test set hp8116a function gen. 4khz, 0v to 2.7v sq. wave rohde & schwarz smt03 100khz, C30dbm AD6122 test bed pd1, pd2 ifin ifout tektronix tds 744a ch 1 with x10 probe ch 2 with coax cable 50 v b. response time from pd1 and pd2 control to if output hp8116a function gen. 4 khz, 0.5v to 2.5v sq. wave rohde & schwarz smt03 100mhz, C30dbm AD6122 test bed agc ifin ifout tektronix tds 744a ch 1 with x10 probe ch 2 with coax cable 50 v a. response time from gain control to if output figure 5. response time setup 10nf 10nf 0.1 m f to spectrum analyzer vreg out 453 v 205 v 453 v 0.1 m f vreg out pull-up inductors chosen for peak response at the test frequency. 10nf 10nf rf source 511 v 383 v 383 v 4:1 ifinn ifinp txopp txopn 1:8 AD6122 figure 2. if amplifiers characterization input and output impedance matches
rev. 0 AD6122 C7C a C40 C140 C130 C120 C110 C100 C90 C80 C70 C60 C50 cl1 1 cu1 ref lev C40dbm center 130.38mhz 519khz/div span 5.19mhz rbw vbw swt 30khz 100khz 2s unit dbm C49.18dbm 130.67458918mhz C33.92dbm C77.32db 77.46db (t1) 1 ch pwr acp up ave low power C dbm figure 6. spectral plot at modulator outputs: acpr frequency C mhz C50 50 350 100 lo leakage C dbc 150 200 250 300 C45 C35 C40 figure 7. modulator lo leakage vs. output frequency output frequency C mhz C15 C20 C40 50 350 100 output desired sideband level C dbm referred to 1k v 150 200 250 300 C25 C30 C35 figure 8. modulator output desired sideband vs. output frequency without roofing filter typical performance characteristicsC output frequency C mhz C30 C45 50 350 100 undesired sideband C dbc 150 200 250 300 C35 C40 figure 9. modulator output undesired sideband vs. output frequency modulator, i = q C dbv C10 C15 C35 C14.0 C2.0 C12.0 modulator output C dbm referred to a 1k v differential load C10.0 C8.0 C6.0 C4.0 C20 C25 C30 figure 10. modulator gain: input (dbv) vs. output (dbm) output frequency C mhz C65 50 350 100 third harmonic C dbc 150 200 250 300 C45 C55 C60 C50 figure 11. modulator third harmonic
rev. 0 AD6122 C8C vgain C v 40 20 C80 0.5 2.5 1.0 gain C db with a 1k v load 1.5 2.0 0 C40 C60 C20 t a = C40 8 c t a = +85 8 c t a = +25 8 c figure 12. if amplifier response curve: gain error vs. vgain, t a = C40 c, +25 c, +85 c vgain C v 45 25 C75 0.5 2.5 0.9 error from predicted valve C db 1.3 1.7 2.1 5 C15 C55 C6.0 C5.0 C35 6.0 5.0 3.0 1.0 C1.0 gain C db C65 C45 C25 C5 15 35 4.0 2.0 0 C4.0 C3.0 C2.0 gain gain error figure 13. if amplifier gain and error vs. vgain vgain C v 5.0 0 C25.0 0.5 2.5 0.9 iip3 C dbm referred to 1k v 1.3 1.7 2.1 C5.0 C15.0 C20.0 C10.0 figure 14. if amplifier input ip3 vs. vgain supply voltage C v C24 C25 C28 2.5 3.7 2.7 iip3 C dbm referred to 1k v 2.9 3.1 3.3 3.5 C26 C27 figure 15. if amplifier input ip3 vs. supply voltage C23 C26 50 350 100 iip3 C dbm referred to 1k v 150 200 250 300 C24 C25 frequency C mhz figure 16. if amplifier input ip3 vs. frequency gain C db 30.0 25.0 5.0 C10.0 40.0 0 noise figure C db 10.0 20.0 30.0 20.0 15.0 10.0 238mhz 313mhz 133mhz figure 17. if amplifier noise figure vs. gain
rev. 0 AD6122 C9C frequency C mhz 40 20 C80 50 350 100 gain C db 150 200 250 300 0 C20 C60 C40 vgain = 2.5v vgain = 2.0v vgain = 1.5v vgain = 1.0v vgain = 0.5v figure 18. if amplifier gain vs. frequency for vgain = 2.5 v, 2.0 v, 1.5 v, 1.0 v a C40 C130 C120 C110 C100 C90 C80 C70 C60 C50 cl1 1 cu1 co co C46.78dbm 130.38000000mhz C31.93dbm C66.95db C68.95db C0.28 db 330.66132265khz (t1) 1 ch pwr acp up ave low ref lev C30dbm center 130.38mhz 600khz/div span 6mhz rbw vbw swt 30khz 300khz 2s unit dbm C30 1 (t1) 1 power C dbm figure 20. acpr of cascaded modulator, 20 db pad and if amplifier: spectral plot vgain C v 18.0 16.0 8.0 0.5 2.5 total current consumption C ma 1.0 1.5 2.0 14.0 12.0 10.0 figure 19. total current consumption vs. vgain
rev. 0 AD6122 C10C theory of operation the cdma transmitter if subsystem (figure 21) consists of an i and q modulator with a divide-by-two quadrature genera- tor, high dynamic range if amplifiers with voltage-controlled gain, a low dropout regulator and power-down control inputs. i and q modulator the i and q modulator accepts differential quadrature base- band inputs from cdma baseband converters. the lo is in- jected at twice the if frequency. a divide-by-two quadrature generator followed by dual polyphase filters ensures 1 quadra- ture accuracy (figure 22). the input stage uses a differential, continuously variable attenuator based on analog devices patented x-amp? topology. this low noise attenuator consists of a differential r-2r ladder network, linear interpolator and a fixed gain amplifier. for 500 mv p-p differential i and q input signals, the output power of the modulator will be C21 dbm referred to 1 k w when the output of the modulator is loaded with a 1 k w differential load. with the maximum input conditions stated above, the modulator outputs are a 225 m a p-p differential current; conse- quently, the output load will greatly affect the output power of the modulator. 180 8 4 2 4 2 polyphase filters i q i q 2 3 if lo input quadrature output to modulator figure 22. simplified quadrature generator circuit the i and q modulator also provides a common mode reference signal at the modcmref pin (pin 21). this voltage is a dc voltage set to 1.408 v when a 2.7 v supply is used. it is used to dc bias the output of the dac that provides i and q inputs to the modulator. if amplifiers and gain control the if amplifiers provide an 86 db linear in db gain control range. the if amplifiers input impedance is 1 k w differential. similar to the i and q modulators output, the if amplifiers output is a differential current, which will vary depending upon the gain control voltage. in order to achieve the specified gain, the output of the if amplifiers should be loaded with a 1 k w differential load. the gain control circuits contain both temperature compensa- tion circuitry and a choice of internal or external reference for adjusting the gain scale factor. the gain control input accepts an external gain control voltage input from a dac. it provides 97 db of gain control range with a nominal 75 db/v scale factor. the external gain control input signal should be a clean signal. it is recommended to filter this signal in order to eliminate the noise that results from the dac. if a noisy signal is used for the gain control voltage, vgain (pin 28), inband and adjacent channel noise peaking can occur at the output of the AD6122. a simple rc filter can be employed, but care should be taken with its design. if too big a resistor is used, a large voltage drop may occur across the resistor, resulting in lower gain than ex- pected (as a result of a lower voltage reaching the AD6122). an rc filter with a 20 khz bandwidth, employing a 1 k w resistor is appropriate. this results in an 8.2 nf capacitor. the resulting circuit is shown in figure 23. note that the input resistance at pin 28 is approximately 100 k w . from baseband converter AD6122 vgain 1k v 8.2nf 109k v figure 23. gain voltage filtering i input q input local oscillator input attenuator low dropout regulator common-mode reference output vreg power- down 1 1.23 v reference output vpos temperature compensation gain control scale factor gain control voltage input gain control reference voltage input transmit output if amplifiers quadrature modulator vcc power- down 2 if amplifier input quadrature modulator output 4 2 AD6122 figure 21. block diagram x-amp is a trademark of analog devices, inc.
rev. 0 AD6122 C11C the AD6122s overall gain, expressed in decibels, is linear in db with respect to the automatic gain control (agc) voltage, vgain (pin 28). either pin 26 (refout), or an external reference voltage connected to refin (pin 27), may be used to set the voltage range for vgain. when the internal 1.23 v reference, refout (pin 26), is connected to refin (pin 27), vgain will control the entire agc range when it is typically set between 0.5 v and 2.5 v. minimum gain occurs at mini- mum voltage on vgain and maximum gain occurs at maxi- mum voltage on vgain. the maximum and minimum gain will not change with a change in voltage at refin. rather, the slope of the gain curve will change as a result of a change in the required range for vgain. figure 24 shows the piecewise linear approximation of the gain curve for the AD6122. minimum gain maximum gain gain C v/v vgain C v figure 24. piecewise linear approximation for the AD6122 gain curve because the minimum and maximum gain from the AD6122 are constant, we can determine the vgain range for a given refin voltage by using equations 1 and 2. minimum gain vgain refin = 04 . (1) maximum gain vgain refin = 2 (2) where maximum gain for the AD6122 is +34 db or 50.1 v/v, and minimum gain is C63 db or 0.708 mv/v, vgain is the gain control voltage applied to pin 28 of the AD6122 and re- fin is the reference input voltage, pin 27. consequently, for any refin we choose, we can calculate the vgain range by rear- ranging and solving equations 1 and 2 for vgain. power-down control the AD6122 can be operated with the if amplifiers and quadra- ture modulator both powered up, both powered down or with the if amplifiers powered up and the modulator powered down. the AD6122 cannot operate with only the modulator powered up. the control is provided via two control pins, pd1 (pin 1) and pd2 (pin 2). table i shows the operating modes of the AD6122. table i. operating modes pd1 pd2 if amp modulator 0 0 on on 0 1 on off 1 0 invalid state invalid state 1 1 off off low dropout regulator the AD6122 incorporates an integrated low dropout regulator. the regulator accepts inputs from 2.9 v to 4.2 v and supplies a constant 2.7 v reference output at pin 5 (ldoc). the 2.7 v signal can be used to provide the dc voltages required for the dvcc (pin 10), txvcc (pin 13) and ifvcc (pin 25) dc supplies. in order to configure the low dropout regulator, an external pass transistor is required. a pnp bipolar junction tran- sistor with a minimum h fe of 100 and a maximum h fe of 300 and a vce sat of C0.4 v is required. in order to use the low dropout regulator, configure the transistor as shown in figure 25. the 18 pf capacitor in figure 25 is used for decoupling the 2.7 v dc signal. in addition to the low dropout regulator, a band-gap voltage reference produces a 1.23 v reference voltage at pin 26 (refout). this reference voltage will be present whenever a 2.7 v dc signal is present on pin ldoc (pin 5). this 1.23 v reference voltage can then be used to provide the gain reference signal required for pin 27 (refin) and the reference voltage for the transmit dacs in a baseband converter. AD6122 ldoe ldoc ldob 18pf 2.9v C 4.2v 2.7v refout 1.23v pass transistor figure 25. configuring the low dropout regulator it is possible to bypass the low dropout regulator on the ad 6122 and use an external regulator instead. in order to bypass the integrated low dropout regulator, connect pins ldoe (pin 3), ldob (pin 4) and ldoc (pin 5) together and then connect them all to the 2.7 v external regulator voltage. this configura- tion is shown in figure 26. even when the low dropout regula- tor is bypassed, the 1.23 v reference voltage at pin refout (pin 26) is still present. from external voltage regulator AD6122 ldoe ldoc ldob refout 1.23v figure 26. configuration for bypassing the low dropout regulator
rev. 0 AD6122 C12C roofing filter because the outputs of the AD6122 modulator are open collec- tor, the parasitic capacitances seen at the output of the modula- tor, and inputs of the if amplifiers, are high enough to create a low-pass filter, which may attenuate the if signal. consequently, the parasitic capacitance must be cancelled by using external inductors to form a parallel resonant circuit. the external in- ductors and the internal parasitic capacitors form what is known as the roofing filter, with the resonant frequency given by equa tion 3. f lc par 0 1 2 = p (3) where f 0 is the if frequency, in hertz, c par is the total parasitic capacitance in farads, and l is the value of external inductors, in henrys. the roofing filter may be composed of the pull-up inductors required on the open collector outputs of the i and q modula- tor. this configuration is shown in figure 27. the 10 nf ca- pacitors are used for ac coupling. AD6122 modopp modopn ifinp ifinn l/2 2c par 2c par attenuator 10nf l/2 10nf parallel resonant circuit 10nf vcc figure 27. roofing filter configuration the attenuator is discussed in the next section entitled measur- ing adjacent channel protection ratio (acpr). in order to confirm whether the roofing filter has been correctly designed, sweep the lo frequency and view the output of the if amplifier on a spectrum analyzer. the signal should peak at the if frequency if the inductor value is correct. the q of the filter should be low enough so that variations in the parasitic capaci- tances should be negligible. the value of inductor required will be a function of the if fre- quency at which we are operating. the values of inductors used during characterization at analog devices are shown in table ii. because the exact value will also be a function of printed circuit board layout, we will have to vary the value from those in table ii to those required for our board. table ii. roofing filter inductor values value of roofing filter if frequency (mhz) inductor (nh) 50C125 470 126C200 150 201C275 68 276C350 27 it should be noted that the roofing filter is only required when cascading the output from the i/q modulator to the input of the if amplifiers. if we are driving into the if amplifiers directly, no roofing filter is required, however, pull-up indu ctors are required in order to set the dc voltage of the open collector modulator outputs. measuring adjacent channel power ratio (acpr) at maximum if gain and specified input conditions (500 mv p-p baseband inputs), the output of the i/q modulator is 11 db greater than the p1db (one db compression point) of the if amplifiers. this configuration maximizes the ratio of signal to lo feedthrough and also maximizes the signal to noise ratio. once these ratios are maximized, we can attenuate the noise, signal and lo feedthrough without affecting the ratios. there- fore, attenuation is required between the i/q modulator and the if amplifiers. in order to determine exactly how much attenuation is required, we must recognize that acpr is a function of the attenuation from the modulator outputs to the if amplifier inputs. as a result, in order to determine how much attenuation is required, we must first know how good an acpr performance is desired. if too much attenuation is applied, the acpr will be very good, but, the if amplifiers output power level will be low, possibly resulting in poor signal to noise ratio and possibly requiring additional amplification external to the AD6122. an appropriate method that can be used to provide the correct amount of attenuation between the modulator outputs and the if amplifier inputs is a simple differential voltage divider. the topology and its design equations are shown in figure 28 and equations 4 and 5. the input impedance of the if amplifiers is typically 1 k w . as a result, if we design resistor r2 to be much less than 1 k w , we can neglect the effects of the if amplifiers input impedance on the attenuator. r2 r1 modopp modopn ifinp ifinn z in r1 rshunt >>r2 AD6122 figure 28. pad topology
rev. 0 AD6122 C13C l r rr = + ? ? ? ? ? ? 20 1 1 1 1 1 22 log / (4) zrr in =+ 21 2 (5) where l is the transducer loss (or loss through the pad) in db and z in is the desired input resistance in ohms. using these equations, we can design the attenuator circuit to provide what- ever amount of attenuation we require. this circuit is very sensitive to parasitic capacitances. as a re- sult, extra care should be taken to ensure minimum and equal printed circuit board transmission lines. we should also try to keep r2 small in order to minimize the effects of printed circuit board parasitic capacitance on loading the output of the pad. in conclusion, we have to develop a system-level acpr budget for our radio, and from that budget determine how much acpr performance we desire from the AD6122. we then need to imple- ment the appropriate attenuation network to get that acpr performance. i q lo modulators 500mv p-p differential 500mv p-p differential 100mv p-p differential 20db attenuator vgain = 2.5v gain = +34db transmit output if amplifiers C21dbm (referred to 1k v ) 252.1mv p-p differential C41dbm (referred to 1k v ) 25.21mv p-p differential C7dbm (referred to 1k v ) 1.263v p-p differential modop ifin z in = 1k v z out = 1k v 1k v 4 2 z in = 1k v vcc figure 29. level diagram level diagram figure 29 is provided to better understand the different voltage levels you can expect to see at different points of the AD6122. it represents the voltage and power levels expected for a maxi- mum input condition of 500 mv p-p at the i and q modulator and maximum gain in the if amplifiers. when trying to make these measurements, a high impedance (10 m w ) active fet probe (for example, the tek p6204, from tektronix) should be used to minimize the effects of loading the circuit with the probe. in order to produce these results, the attenuator is designed to have a 1 k w input impedance and the output of the if amplifi- ers are loaded with 1 k w . the roofing filter is designed to reso- nate the parasitic capacitance at the if frequency.
rev. 0 AD6122 C14C input interfaces the AD6122 interfaces to cdma baseband converters provid- ing either if or baseband outputs. the baseband input is pro- vided by direct connection of the baseband converters baseband output to the baseband input of the AD6122 (figure 30). the if amplifiers gain control is provided by connection of the transmit agc dacs output on the baseband converter, through a low-pass filter to the vgain pin (pin 28) on the AD6122. gain control scale factor low dropout regulator vcc temperature compensation txvcc ifinn pd1 4 2 AD6122 pd2 ifinp tx agc dac cdma baseband ic ext ref in i output i output vcm ref in q output q output ifvcc ifgnd iipp iipn qipn qipp modcmref modopn modopp refout refin vgain i q txopn txopp ifgnd dvcc loipn loipp dgnd ldognd ldoc ldob ldoe vcc vcc figure 30. typical connections to baseband ic using i and q inputs
rev. 0 AD6122 C15C AD6122 evaluation boards, rev. b the AD6122 evaluation board (rev. b) consists of an AD6122, i/o connectors, a 20-pin dual header, 2-pin headers and four ad830 high speed video difference amplifiers. it allows the user to evaluate the AD6122s if amplifier and modulator together or separately. because the AD6122 may be used at any if from 50 mhz to 350 mhz, pads are provided on the loipp input, txop output, modop output and ifip inputs to allow the user to add matching networks. the board is configured for an if frequency of 130.38 mhz when shipped. the ad830s are used to provide single-ended to differential conversion and the appropriate phase shift for the i and q data input pins. as a result, a single-ended signal generator can be used to generate these signals. in order to test the power-down modes of the AD6122, locate the two pin headers on the AD6122 evaluation boards labeled pd1 and pd2. by open-circuiting the pins labeled pd1, the if amplifiers power down. by open-circuiting the pins labeled pd2, the modulator powers down. note that the if amplifiers and modulator are powered down unless the pins on the two pin headers, pd1 and pd2, are short circuited. the if input port impedance match used during characteriza- tion of the AD6122 at analog devices is as follows: ifinp ifinn AD6122 signal generator 511 v 383 v 383 v 50 v 1k v 1:8 figure 31. if input port impedance match used during characterization at adi this is a broadband lossy match used for characterization over the 50 mhz to 350 mhz frequency range. all dbm references in the characterization data collected using this match are refer- enced to 1 k w . note that the 1:8 ratio in figure 32 is an imped- ance ratio and not a voltage ratio. the if output port impedance match used during characteriza- tion at analog devices is as follows: txopp AD6122 spectrum analyzer 205 v 453 v 453 v 50 v 1k v 4:1 txopn figure 32. if output port impedance match used during characterization at adi this is a broadband lossy output match for the 50 mhz to 350 mhz f requency range. the 4:1 ratio in figure 32 is an impedance ratio and not a voltage ratio. as shipped, the board is configured as follows: 1. j1 is open and j2 is shorted. this enables the ldo regulator. the external pnp transistor should remain in place even when the regulator is bypassed (the pin ldob is pulled up by the transistor). 2. x11, x25, x18 and x26 are shorted and x12, x14, x19 and x21 are opened in order to connect the output of the modulator to the input of the if amplifiers. 3. l4 and l5, the roofing filter components are optimized for an if frequency of 130.38 mhz. 4. r14, r15 and r16 set the attenuation between the modula- tor outputs and the if amplifier inputs to 20 db. 5. pd1 and pd2 are pulled low by the jumpers on the two pin headers. to power down the chip, set pd1 and pd2 high by removing the jumpers. in order to look at the modulator and if amplifiers separately, disconnect the output of the modulator from the input of the if amplifiers. this is accomplished by short circuiting x12, x14, x19 and x20 and open circuiting x11, x18, x25 and x26. table iii describes the high frequency signal connectors on the AD6122 customer sample boards. table iii. evaluation board sma signal connector description connector description i ch i modulator input. 250 mv p-p into 50 w termination, dc coupled. the level shifting and phase splitting is done on board by the ad830 amplifiers. q ch q modulator input. 250 mv p-p into 50 w termination, ac coupled. the level shifting and phase splitting is done on board by the ad830 amplifiers. modop modulator output. the differential-to-single ended conversion is performed by a balun on the board. impedance matched to 50 w for 130.38 mhz if frequency. ifip if amplifier input. single-ended-to-differential conversion performed by a balun on board. impedance matched to 50 w for 130.38 mhz if frequency. txop if amplifier output. differential-to-single- ended conversion performed by a balun on board. impedance matched to 50 w for 130.38 mhz if frequency. loipp local oscillator positive input at 2 if frequency.
rev. 0 AD6122 C16C table iv lists the co nnections for the 20-pin power-supply connector. table iv. 20-pin power supply connection information pin # function 1 vpos for AD6122; 2.9 v to 4.2 v using regulator; 2.7 v to 4.2 v bypassing regulator. 2 vpos for AD6122; 2.9 v to 4.2 v using regulator; 2.7 v to 3.6 v bypassing regulator. 3 ground. 4 ground. 5 ground. 6 regulated output or input voltage; connects to pin 5 on AD6122. 7 ground. 8 ground. 9 ground. 10 ground. 11 ground. 12 pd1; power-down 1 input. 13 ground. 14 1.23 v reference voltage from AD6122. 15 ground. 16 vgain; gain control voltage input. 17 C15 v supply for ad830 differential amplifier. 18 +15 v supply for ad830 differential amplifier. 19 modcmref; common-mode reference output for baseband converter common-mode reference input. 20 pd2; power-down 2 input. a schematic diagram of the evaluation board is on the next two pages.
rev. 0 AD6122 C17C 1 3 5 7 9 11 13 2 4 6 8 10 12 14 15 19 17 16 20 18 21 22 23 24 25 26 27 28 vreg_out q1 fmmt4403ct-nd vpos 2.9v C 4.2v loipp x1 l2 220nh x8 0 v x6 3pf x5 100nh 1:8 t1 txop dvcc vgain refout ifvcc vreg_out c24 0.1 m f c3 10nf x3 x10 0 v x4 x7 x9 c1 10nf x2 0 v l3 220nh c25 10nf vcc pd1 pd2 ldoe ldob ldoc ldognd dgnd loipp loipn dvcc txopp txopn txvcc ifgnd modcmref iipn iipp ifgnd ifvcc refout refin vgain qipn qipp modopp modopn ifinp ifinn AD6122 c2 10nf c23 18pf pd1 pd2 j1 j2 0 v txvcc c11 10nf c10 10nf c9 10nf x12 x13 x14 c30 l6 x11 0 v r13 x25 0 v r16 r15 r14 x19 x20 x21 x18 0 v x26 0 v c8 10nf iipp iipn qipn qipp modcmref c29 10nf ifip r14 = 442 v r15 = 100 v r16 = 442 v l4 180nh c27 10nf l5 180nh c26 10nf vreg_out r12 0 v 8:1 x17 x24 x15 4pf t2 x16 100nh modop x23 27nh 8:1 t3 x22 56nh c4 10nf vcc c28 10nf figure 33. schematic diagram of the evaluation board
rev. 0 AD6122 C18C 2 5 ad830 ich c16 0.1 m f modcmref a=1 vC1 1 3 4 8 7 2 5 ad830 a=1 1 3 4 +15v c17 0.1 m f 8 7 to iipp r7 50 v r6 50 v modcmref c18 0.1 m f to iipn u2 u3 c15 0.1 m f +15 v r8 50 v C15v C15v soic package p1 3 7 11 15 19 1 5 9 13 17 l1 470nh refout vgain from vpos 2.9vC4.2v vreg_out +15v pd2 p2 4 8 12 16 20 2 6 10 14 18 C15v modcmref r4 10k v r5 10k v pd1 pd2 vpos pd1 c6 18pf r1 10 v c13 0.01 m f c5 18pf r2 10 v c12 0.01 m f c7 18pf r3 10 v c14 0.01 m f to dvcc to ifvcc to txvcc vreg out 2 5 ad830 qch c20 0.1 m f modcmref a=1 1 3 4 8 7 2 5 ad830 a=1 1 3 4 +15v c21 0.1 m f 8 7 to qipp r10 50 v r9 50 v modcmref c22 0.1 m f to qipn u4 u5 c19 0.1 m f +15v r11 50 v C15v C15v soic package notes: 1. to use the ldo regulator, short j2 and open j1. 2. to bypass the regulator, short j1 and open j2 3. to connect the output of the modulator to the input of the if amp, short j5 and j6. to test the modulator and the if amp separately open j5 and j6. indicates a 50 v trace. 4. vC1 vC1 vC1 vC1 vC1 vC1 vC1 figure 34. schematic diagram of the evaluation board
rev. 0 AD6122 C19C outline dimensions dimensions shown in inches and (mm). 28-lead ssop (rs-28) 28 15 14 1 0.407 (10.34) 0.397 (10.08) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.79) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.015 (0.38) 0.010 (0.25) 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) 8 0 c3437C8C10/98 printed in u.s.a.

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